The present invention relates to an isolation interface with a capacitive barrier comprising, at the input end of the capacitive barrier, an input circuit with differential outputs for a first and a second logical output signals that are complementary to one another and are replicas of a transmitted input signal, and a first and a second barrier capacitors for the first and the second logical signals, respectively, and, at the output end of the capacitive barrier, an output circuit with inputs for a first and a second logical signal transmitted across the capacitive barrier, the said output circuit comprising a first and a second voltage comparators. The present invention also relates to a method for transmitting a signal by means of such isolation interface.
An isolation interface renders possible data transmitting, normally in the digital form, between two or several circuits having separate supplying voltage sources. Since these circuits have no common mass connection, between them a voltage difference results, which may attain even a value of several kilovolts and may vary very fast so that the voltage difference variation rate attains the order of magnitude of 10 kV/xcexcs.
In isolation interfaces the transient electrical currents between circuits are inhibited by means based on different physical principles.
The most common one is an optical isolation interface. An input circuit light emitting diode transforms an electrical signal into light pulses that are transformed by an output bipolar transistor back into an electrical signal. Except in the high-price range, the optical isolation interface makes possible only a relatively low data transmission rate on the level of several megahertz and the current consumption of said elements thereof is rather high.
A fast acceptance has been gained by an interface with a magnetic coupling between a magnetic loop and a magnetic field sensor. The magnetic unit can be advantageously fabricated on a single substrate for an integrated circuit; the magnetic loop is a conductive track that is, through a silicon dioxide, separated from the elements that are connected to another voltage supply; the magnetic field sensor is a magneto-resistor. A data transmission at a rate up to 50 MHz is made possible. When appropriately constructed, its current consumption is lower than that of an optical isolation interface. However, it is fabricated according to a relatively pretentious technology since the magneto-resistor is added to the integrated circuit in demanding and high-cost technological steps.
There are also known isolation interfaces using a capacitive coupling. In a basic embodiment two opposite-in-phase digital output signals U1oxc2x1, being replicas of a transmitted input signal Ui, of an input circuit A1xe2x80x2 are conducted to a first plate of either barrier capacitor Cxe2x80x2xc2x1 (FIG. 1). From their second plate digital input signals U2ixc2x1 are conducted to an output circuit A2xe2x80x2, at whose output a transmitted output signal Uout appears. The high and low potential of a supplying voltage source for the input circuit A1xe2x80x2 are U1+ and U1xe2x88x92, respectively, as well as U2+ and U2xe2x88x92, respectively, for the output circuit A2xe2x80x2. A second plate of either barrier capacitor Cxe2x80x2xc2x1 is through a capacitor Cxe2x80x3xc2x1 s as well as through a resistor Rxe2x80x2xc2x1, each of said connections representing a voltage divider, namely the first one for a time varying signal and the second one for a direct voltage signal, connected to a common potential of the supplying voltage source for the output circuit A2xe2x80x2. The time development of the input signal voltage Ui with regard to the said common potential is represented in a first window of FIG. 2; at t=90 ns the potential difference between the supplying source for the first circuit A1xe2x80x2 and the supplying source for the second circuit A2xe2x80x2, resulting in a voltage on the capacitors Cxe2x80x2+ and Cxe2x80x2xe2x88x92, started to grow and reached the 50 V level. By a full line and a dashed line in a second and third window of FIG. 2 there are represented time developments of the opposite-in-phase digital signals U1oxc2x1 and U2ixc2x1. In a fourth window of FIG. 2, however, the transmitted output signal Uout is represented, whose frequency is equal to the frequency of the input signal Ui. Direct and low-frequency potential differences are limited in magnitude only by the break-down strength of the capacitors Cxe2x80x2+ and Cxe2x80x2xe2x88x92. The resistors Rxe2x80x2xc2x1 ensure that, as regards the magnitude, also at low frequencies the input signals U2ixc2x1 are always within the range of allowed input voltages for voltage comparators in the circuit A2xe2x80x2. In numerous applications, however, the described interface must also function under fast variations of the potential difference between the supplying source of the first circuit A1xe2x80x2 and the supplying source of the second circuit A2xe2x80x2. The necessary lowering of the high-frequency signals U2ixc2x1 is reached by an appropriate ratio of the capacitances of the capacitors Cxe2x80x2+, Cxe2x80x3+ and Cxe2x80x2xe2x88x92, Cxe2x80x3xe2x88x92, respectively. This ratio must be 1:500 if the described interface should manage a voltage difference of 1 kV at a tolerated input voltage of 2 V for the voltage comparator. Such ratio, however, also lowers the amplitude of the signal replicas U2ixc2x1 of the input signal Ui at the input to the circuit A2xe2x80x2 to only a few millivolts. Hereby the signal transmission rate is retarded or even made impossible because the signal amplitudes are already in the range of characteristic offset voltages of a voltage comparator. Hence, if the insensitivity to a fast variation of the potential difference between the two supplying sources is ensured by the described interface it is not possible at the same time to ensure the fastest possible data transmission.
In the U.S. Pat. No. 4,835,486 there is actually disclosed an interface provided with a capacitive coupling suitable for to a digital signal transmission up to the frequency of 1.5 MHz. A differentiating unit at the capacitive barrier is used, however, the time constant of the differentiating unit is 9 ns. So the time constant is longer than the characteristic time of variations of a signal replica at the output of a first circuit in front of the capacitive barrier and therefore the amplitude of the signal replica has to be limited by a diode limiter at an input of a circuit behind the capacitive barrier. Further, an input amplifier in the circuit behind the capacitive barrier transforms the signal pair into one single signal. Hereby the pulse width is additionally distorted since a complete symmetry in the amplifier output signal variation can never be provided for.
In the isolation interface with the capacitive coupling a limitation is immanent that no non-varying-in-time information can be transmitted thereby because of the capacitive barrier. Therefore after a switching-on or, when for a long time no change of the output signal of the circuit at the input end of the capacitive barrier has taken place, after a first change in the logical state of the output signal of the circuit at the output end of the capacitive barrier, the signal at the output end of the capacitive barrier is put into the right logical state, that is into the logical state of the said output signal.
Consequently, the technical problem to be solved by the present invention is to find such a low price interface with a capacitive barrier and a method for transmitting a signal by means of such an isolation interface that between circuits at the input end and at the output end of the capacitive barrier even the fastest data transmission will be made possible, whereat in the circuit at the input end a signal will be formed which will be the most appropriate input signal for the circuit at the output end and the transmission will be insensitive to a very fast variation of the electrical potential difference, even in the range of 10 kV/xcexcs, between the supplies of the said input and output circuits, and at the same time the isolation interface with the capacitive barrier should be completed so that the receiving circuit will pass to the right logical state immediately after its switching-on and it will stay in the right state also when for a long time no change of the output signal of the circuit at the input end of the capacitive barrier has taken place.
The technical problem is solved by an isolation interface with a capacitive barrier, comprising
at the input end of the capacitive barrier, an input circuit with differential outputs for a first and a second logical output signals, respectively, that are replicas of a transmitted input signal and are complementary to one another,
a first and a second barriers capacitor for the first and second logical signals, respectively,
at the output end of the capacitive barrier an output circuit with inputs for a first and second logical input signal, respectively, that are complementary to one another, which output circuit comprises a first and a second voltage comparators,
the isolation interface of the invention with the capacitive barrier being characterized in
that in the input circuit a first and a second integrating units are provided, across which the first logical output signal and the second logical output signal, respectively, passed and by means of whose time constants the slope rates of the edges of the signals or the rising and falling-off times of the signals were adjusted,
and that to an output terminal of the first and the second barrier capacitors on the one hand and to a common potential terminal of the output circuit on the other hand such a first resistor and a second resistors, respectively, are connected,
that the time constant of a first differentiating unit made of the first barrier capacitor and of the first resistor
and the time constant of the second differentiating unit made of the second barrier capacitor and of the second resistor are shorter than the rising and falling-off times of the logical output signals being the replicas of the transmitted input signal.
The isolation interface of the invention with a capacitive barrier is further characterized in that the first logical input signal and the second logical input signal of the output circuit are conducted directly to a first and a second inputs, respectively, of the first voltage comparator as well as to a second and first inputs, respectively, of the second voltage comparator and that an output of the first voltage comparator and an output of the second voltage comparator are connected to inputs of a flip-flop, whose output is an output of the isolation interface with the capacitive barrier.
The isolation interface of the invention with a capacitive barrier is completed so that an input of the basic isolation interface of the invention with a capacitive barrier is connected to a control input of a pulse-width modulator, to whose second input a constant frequency signal is uninterruptedly conducted and whose output is connected to an input of an auxiliary isolation interface provided for transmission over an auxiliary communication channel, and that the output of the basic isolation interface with the capacitive barrier and an output of the auxiliary isolation interface for the transmission over the auxiliary communication channel are connected to inputs of a decision logical circuit that provides for a correct logical state of the signal transmitted by the basic isolation interface with the capacitive barrier and that an output of the decision logical circuit is the output of the isolation interface with the capacitive barrier.
The completed isolation interface of the invention with a capacitive barrier is further characterized in that individual output end units of the basic isolation interface with the capacitive barrier are turned on or off depending upon the presence of the modulated signal at the output of the auxiliary isolation interface for the transmission over the auxiliary communication channel.
The technical problem is also solved by a method for transmitting a signal through an isolation interface with a capacitive barrier, the method of the invention being characterized in that in an input circuit of the isolation interface with the capacitive barrier by means of the integration with an appropriate time constant the slope rates of the edges or the rising and falling-off times of signal replicas of the transmitted input signal are adjusted and that the said signal replicas are differentiated in a first differentiating unit and a second differentiating unit, respectively, of the capacitive barrier and that the time constants of the first and the second differentiating units are shorter than the rising and falling-off times of the signal replicas of the transmitted input signal.
The method of the invention for transmitting of signal through the isolation interface with the capacitive barrier is further characterized in that signals of the derivatives generated in the differentiating units of the capacitive barrier are conducted directly to two voltage comparators comprised in an output circuit of the isolation interface with the capacitive barrier.
The completed inventive method for transmitting a signal through the isolation interface with the capacitive barrier is characterized in that, besides transmitting the input signal through a basic isolation interface with the capacitive barrier, there is uninterruptedly performed a transmitting of a constant frequency signal that is pulse-width-modulated by the transmitted input signal, through an auxiliary isolation interface for transmission over an auxiliary communication channel is performed and that, with regard to the modulation of the transmitted pulse-width-modulated signal, the logical state of an output signal transmitted by the isolation interface with the capacitive barrier is adjusted.